This paper proposes the design of a 6-bit single-ended SAR ADC with a variable sampling rate at a maximum achievable speed of 50 MS/s. The SAR ADC utilizes the split capacitor array DAC with a non-conventional split-capacitor value. The influence of switches in the capacitive DAC on the ADC’s non-linearity is analysed. According to the fulfilled analysis the recommendations for switches and capacitor array dimensioning are given to provide a minimum differential non-linearity (DNL). At a sampling rate of 50 MS/s, the SAR ADC achieves an ENOB of 5.4 bit at an input signal frequency of 1 MHz and consumes 1.2 mW at a 1.8 V power supply, resulting in an energy efficiency of 568 fJ/conv.-step. The SAR ADC was simulated with parasitics in a standard 180nm CMOS process.
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